1. Field of the Invention
The present invention relates to a semiconductor device manufacturing mask substrate and a semiconductor device manufacturing method, and particularly to a semiconductor device manufacturing mask substrate for simply manufacturing a semiconductor device which less provides a residual film-thickness difference subsequent to a polishing process of an interlayer insulating film, which occurs due to the difference in pattern density between wiring patterns of the semiconductor device, and a semiconductor device manufacturing method.
2. Description of the Related Art
With high integration of a semiconductor device, densification and multilayering of internal wirings have been put forward in recent years. Light used for exposure, which is used in photolithography, has been advanced in wavelength shortening. When the difference between pattern densities set every semiconductor device manufacturing mask substrates (hereinafter called simply masks) is large in cooperation with lack of a focal depth due to its advance, a problem arises in that etching at wiring fabrication using masks is brought into imperfection and etching conditions must be changed depending on masks to be used. Therefore, when the difference occurs between the pattern densities set every masks, a method of inserting pseudo patterns (also called dummy patterns) except for actual patterns and uniforming etching conditions has been used. Incidentally, the pattern density in the present specification means a ratio of an area for the whole mask to an area in which patterns are laid out within the mask.
As to the pseudo patterns, various techniques have been adopted for how to insert them, according to a pattern form of each mask. As one example of the pattern form of the mask, there is known one which comprises a device section in which patterns for forming thin gate wirings are disposed without a bias, and a TEG (Test Elemental Group) section in which the layout of patterns is biased like insertion of a capacity-measuring large pattern (e.g., a square whose one side is about 100 μm) and the like, and a pattern placement-free area exists. In such a mask, the pseudo patterns are inserted into areas free of the placement of the patterns for the TEG section.
Meanwhile, a high-density plasma CVD (High Density Plasma-Chemical Vapor Deposition: hereinafter called HDP-CVD) oxide film or the like, i.e., an interlayer insulating film is formed over the mask after the formation of the wirings using the mask. The interlayer insulating film varies in deposited-film thickness according to forms of underlying wirings. The interlayer insulating film has a feature that when, for example, local irregularities occur in the surface of the interlayer insulating film depending on irregularities of each underlying thin wiring pattern, and thin wiring patterns are extensively inserted without their bias as in the case of the device section, minus sizing is effected thereon and hence the amount of deposition thereof is reduced, whereas the interlayer insulating film is deposited thick in a large-pattern existing area as in the case of the TEG section. Therefore, a process for flattening the interlayer insulating film is performed by chemical mechanical polishing (hereinafter called CMP) to reduce the irregularities of the surface of the interlayer insulating film and its step.
The flattening of the interlayer insulating film by CMP referred to above is effective for the device section or the like with the thin wirings being placed without their bias, because the local irregularities of the interlayer insulating film are lessened. However, the flattening is not so effective for the TEG section or the like with the large pattern being placed therein, in order to reduce a difference (residual film-thickness difference) between the same section and a portion slow in polishing rate and thin in film thickness as in the case of the device section or the like.
When the residual film-thickness difference (hereinafter called a global step) subsequent to the CMP exists, failures such as a layer-to-layer short, a wiring-to-wiring short or its open, etc. are apt to occur when a material film is further formed on an upper layer, thus leading to reductions in yield and reliability. Therefore, a request for reducing the global step has been made. However, a problem arises in that due to the insertion of the pseudo patterns into the TEG section, further non-uniformity in wiring patterns occurs between the device section and the TEG section, thus increasing the global step.